The identification of specific features on a modern integrated circuit chip is extremely difficult given the small physical sizes of the electrical components of the circuits, the similarity in appearance of most components, and their vast numbers. It is expected that the sizes of individual components will continue to shrink and the number of components will continue to increase. Device dimensions of the order of 0.1 microns, and densities in excess of 10,000,000 gates per chip will soon be common in logic chips. An additional complication arises from the fact that the circuits are not designed spatially, but rather logically and schematically. The physical layout of these circuits is done automatically as a complex computerized optimization program following a set of design rules. Therefore, even the designers of the individual parts of the circuit do not necessarily have direct knowledge of the physical layout of their modules. Since chip sizes are of the order of 2 centimeters while individual component placements involve distances on the scale of 0.2 microns, location of an individual component with respect to the edges of the chip can require accuracy in dead reckoning of 1 part in 100,000. Such accuracy is difficult to achieve through simple passive mechanical systems. Similarly, given the complexities of wiring on modern chips, following physical paths from known input and output drivers to a specific device is also extremely difficult and can involve substantial amounts of time. Placement of alignment marks and identifiers such as labels for individual devices is possible but adds complexity to the fabrication and design, and can sacrifice economically valuable area.
Thus, it would be desirable for designers of large scale integrated circuits to be able to precisely identify the position of a particular device on the actual chip if, for instance, it was thought to produce an error in the chip's operation. Alternatively, if it were found that a particular point in a complex circuit were generating an erroneous signal, understanding of the error would require knowledge of the identity of the particular device at that point. In particular, we have recently demonstrated an all optical technique for imaging the switching activity in a switch. We have shown how electrical errors in the operation of a chip could be detected by this technique. It produces an image of the chip which highlights positions where incorrect switching activity occurs. See U.S. patent application Ser. No. 09/026,287, filed Feb. 19, 1998, entitled "Image Processing Methods for Optical Detection of Dynamic Errors in Integrated Circuits", now U.S. Pat. No. 6,172,512 filed on even date herewith. However, full use of this error image requires the ability to map the image onto the actual device positions on the chip. The ability to quickly and precisely identify the devices operating at locations producing faulty imaging signals would allow rapid redesign, resulting in a reduced time to bring fully functional chips to market. Spatial identification of individual devices responsible for operational errors would simplify the process by which faults and failures are analyzed. Clearly, a need has arisen for a technique that would allow any active site on the chip to broadcast its location through an externally detectable signal that could be localized to the site in question. Such a technique would be especially valuable in conjunction with imaging tools which would create pictures of the electrical activity of different points in the chip, and whose interpretation would critically depend on the ability to register the experimentally derived "images" with the layout of devices on the chip.
Commonly owned and copending U.S. patent application Ser. No. 08/683,837, filed Jul. 18, 1996, entitled NONINVASIVE OPTICAL METHOD FOR MEASURING INTERNAL SWITCHING AND OTHER DYNAMIC PARAMETERS OF CMOS CIRCUITS, filed Jul. 18, 1996 , now U.S. Pat. No. 5,,940,545 is incorporated herein by reference.